Arastu Systems Transmission Control Protocol/ Internet Protocol (TCP/IP) Hardware Accelerator is a highly configurable and module soft IP core, specifically designed for FPGA applications. The solution delivers reliable, end to end network communications on Ethernet Networks, by acting as a TCP server for send/receive of TCP/IP at high bandwidth and low latency. The accelerator is FPGA Synthesizable and is available in multiple variants as per the target application.

• Supports TCP/IP protocol suite with TCP in Server & Client Mode
• Supports multiple TCP Sockets as per application needs
• 10M/100M1G/10G/25G/40G Ethernet Connectivity
• Supports ARP with auto-update privilege
• Multiple entries ARP Table
• RARP or DHCP for auto IP Address Acquisition
• ICMP for Echo Request/Response (Ping)
• TCP acknowledgment piggy backing
• Pause frame detection for Flow Control
• TCP Packet Retransmission
• Supports undeliverable datagram discarding on IP layer
• Header checksums in IPv4 (RFC791) and TCP (RFC793)

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